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00026 #ifndef _QORE_MACHINE_MACROS_H
00027 #define _QORE_MACHINE_MACROS_H
00028
00029 #define STACK_DIRECTION_DOWN 1
00030
00031 #ifdef __GNUC__
00032 #ifdef __LP64__
00033
00034 #define HAVE_ATOMIC_MACROS
00035 #define HAVE_CHECK_STACK_POS
00036
00037
00038 #define ia64_cmpxchg4_acq(ptr, new, old) ({ \
00039 unsigned long ia64_intri_res; \
00040 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
00041 asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
00042 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
00043 (int)ia64_intri_res; \
00044 })
00045
00046 static __inline__ int ia64_atomic_add (int i, volatile int *v) {
00047 int old, vnew;
00048
00049 do {
00050 old = *v;
00051 vnew = old + i;
00052 } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
00053 return vnew;
00054 }
00055
00056 static __inline__ int ia64_atomic_sub (int i, volatile int *v) {
00057 int old, vnew;
00058
00059 do {
00060 old = *v;
00061 vnew = old - i;
00062 } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
00063 return vnew;
00064 }
00065
00066 static inline void atomic_inc(volatile int *a) {
00067 ia64_atomic_add(1, a);
00068 }
00069
00070
00071 static inline int atomic_dec(volatile int *a) {
00072 return !ia64_atomic_sub(1, a);
00073 }
00074
00075 static inline size_t get_stack_pos() {
00076 size_t addr;
00077 asm volatile ("mov %0=sp" : "=r" (addr));
00078 return addr;
00079 }
00080
00081 static inline size_t get_rse_bsp() {
00082 size_t addr;
00083 asm volatile ("mov %0=ar.bsp" : "=r" (addr));
00084 return addr;
00085 }
00086
00087 #endif // #ifdef __LP64__
00088 #endif // #ifdef __GNUC__
00089
00090 #ifdef __HP_aCC
00091 #ifdef __LP64__
00092
00093 #define HAVE_ATOMIC_MACROS
00094 #define HAVE_CHECK_STACK_POS
00095
00096
00097 extern "C" void atomic_inc(int *v);
00098 extern "C" int atomic_dec(int *v);
00099 extern "C" size_t get_stack_pos();
00100 extern "C" size_t get_rse_bsp();
00101
00102 #endif // #ifdef __LP64__
00103 #endif // #ifdef __HP_aCC
00104
00105 #endif // #ifndef _QORE_MACHINE_MACROS_H
00106